1. Field of the Invention
The invention relates to chip package technology, and in particular to a stacked chip package and methods for forming the same.
2. Description of the Related Art
The chip packaging process is an important step in the fabrication of an electronic product. Chip packages not only protect the chips therein from outer environmental contaminants, but also provide electrical connection paths between electronic elements inside and outside of the chip packages.
A conventional chip package having sensing functions, such as a fingerprint-recognition chip package shown in FIG. 1, includes a fingerprint-recognition chip 520 on a printed circuit board 510. Wires 530 are electrically connected between a signal pad region of the fingerprint-recognition chip 520 and the printed circuit board 510. The fingerprint-recognition chip 520 and the wires 530 are covered by an encapsulant layer 540. Since the wires 530 protruding from an upper surface of the fingerprint-recognition chip 520 are protected by the encapsulant layer 540, the thickness of the encapsulant layer 540 is limited by the height of the wires 530. In order to prevent sensitivity of a sensing region 523 in the center of the fingerprint-recognition chip 520 from being affected by the thick encapsulant layer 540, the thick encapsulant layer 540 covers the periphery of the fingerprint-recognition chip 520 and exposes the sensing region 523. Therefore, the chip package cannot have a flat surface above the fingerprint-recognition chip 520 and the size of the chip package cannot be further reduced. In addition, since the wires 530 are adjacent to the edges of the fingerprint-recognition chip 520, they easily contact the edges during the bonding process which may result in a short circuit or a broken circuit, thereby reducing the yield of the chip package.
Thus, there exists a need in the art for development of a stacked chip package and methods for forming the same capable of reducing the thickness of the encapsulant layer thereby improving sensitivity of the stacked chip package and providing a stacked chip package having a flat contacting surface and a smaller size.